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Cleanup

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master
Mark Qvist 2 months ago
parent 217db4bcd3
commit eb168d4734
6 changed files with 348 additions and 705 deletions
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  1. 829
      sx126x.cpp
  2. 5
      sx126x.h
  3. 84
      sx127x.cpp
  4. 5
      sx127x.h
  5. 101
      sx128x.cpp
  6. 21
      sx128x.h

829
sx126x.cpp
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sx126x.h
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@ -1,9 +1,6 @@
// Copyright (c) Sandeep Mistry. All rights reserved. // Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
// Licensed under the MIT license. // Licensed under the MIT license.
// Modifications and additions copyright 2024 by Mark Qvist
// Obviously still under the MIT license.
#ifndef SX126X_H #ifndef SX126X_H
#define SX126X_H #define SX126X_H

84
sx127x.cpp
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@ -1,9 +1,6 @@
// Copyright (c) Sandeep Mistry. All rights reserved. // Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
// Licensed under the MIT license. // Licensed under the MIT license.
// Modifications and additions copyright 2024 by Mark Qvist
// Obviously still under the MIT license.
#include "Boards.h" #include "Boards.h"
#if MODEM == SX1276 #if MODEM == SX1276
@ -81,10 +78,7 @@ extern SPIClass SPI;
sx127x::sx127x() : sx127x::sx127x() :
_spiSettings(8E6, MSBFIRST, SPI_MODE0), _spiSettings(8E6, MSBFIRST, SPI_MODE0),
_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN),
_frequency(0), _frequency(0), _packetIndex(0), _preinit_done(false), _onReceive(NULL) { setTimeout(0); }
_packetIndex(0),
_preinit_done(false),
_onReceive(NULL) { setTimeout(0); }
void sx127x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); } void sx127x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); }
void sx127x::setPins(int ss, int reset, int dio0, int busy) { _ss = ss; _reset = reset; _dio0 = dio0; _busy = busy; } void sx127x::setPins(int ss, int reset, int dio0, int busy) { _ss = ss; _reset = reset; _dio0 = dio0; _busy = busy; }
@ -123,7 +117,6 @@ bool sx127x::preInit() {
} }
if (version != 0x12) { return false; } if (version != 0x12) { return false; }
_preinit_done = true; _preinit_done = true;
return true; return true;
} }
@ -144,8 +137,6 @@ uint8_t ISR_VECT sx127x::singleTransfer(uint8_t address, uint8_t value) {
int sx127x::begin(long frequency) { int sx127x::begin(long frequency) {
if (_reset != -1) { if (_reset != -1) {
pinMode(_reset, OUTPUT); pinMode(_reset, OUTPUT);
// Perform reset
digitalWrite(_reset, LOW); digitalWrite(_reset, LOW);
delay(10); delay(10);
digitalWrite(_reset, HIGH); digitalWrite(_reset, HIGH);
@ -153,19 +144,16 @@ int sx127x::begin(long frequency) {
} }
if (_busy != -1) { pinMode(_busy, INPUT); } if (_busy != -1) { pinMode(_busy, INPUT); }
if (!_preinit_done) { if (!preInit()) { return false; } }
if (!_preinit_done) {
if (!preInit()) { return false; }
}
sleep(); sleep();
setFrequency(frequency); setFrequency(frequency);
// set base addresses // Set base addresses
writeRegister(REG_FIFO_TX_BASE_ADDR_7X, 0); writeRegister(REG_FIFO_TX_BASE_ADDR_7X, 0);
writeRegister(REG_FIFO_RX_BASE_ADDR_7X, 0); writeRegister(REG_FIFO_RX_BASE_ADDR_7X, 0);
// set LNA boost and auto AGC // Set LNA boost and auto AGC
writeRegister(REG_LNA_7X, readRegister(REG_LNA_7X) | 0x03); writeRegister(REG_LNA_7X, readRegister(REG_LNA_7X) | 0x03);
writeRegister(REG_MODEM_CONFIG_3_7X, 0x04); writeRegister(REG_MODEM_CONFIG_3_7X, 0x04);
@ -178,20 +166,13 @@ int sx127x::begin(long frequency) {
return 1; return 1;
} }
void sx127x::end() { void sx127x::end() { sleep(); SPI.end(); _preinit_done = false; }
sleep();
SPI.end();
_preinit_done = false;
}
int sx127x::beginPacket(int implicitHeader) { int sx127x::beginPacket(int implicitHeader) {
standby(); standby();
if (implicitHeader) { if (implicitHeader) { implicitHeaderMode(); }
implicitHeaderMode(); else { explicitHeaderMode(); }
} else {
explicitHeaderMode();
}
// Reset FIFO address and payload length // Reset FIFO address and payload length
writeRegister(REG_FIFO_ADDR_PTR_7X, 0); writeRegister(REG_FIFO_ADDR_PTR_7X, 0);
@ -248,30 +229,25 @@ int ISR_VECT sx127x::packetRssi(uint8_t pkt_snr_raw) {
} }
int ISR_VECT sx127x::packetRssi() { int ISR_VECT sx127x::packetRssi() {
int pkt_rssi = (int)readRegister(REG_PKT_RSSI_VALUE_7X) - RSSI_OFFSET; int pkt_rssi = (int)readRegister(REG_PKT_RSSI_VALUE_7X) - RSSI_OFFSET;
int pkt_snr = packetSnr(); int pkt_snr = packetSnr();
if (_frequency < 820E6) pkt_rssi -= 7;
if (pkt_snr < 0) {
pkt_rssi += pkt_snr;
} else {
// Slope correction is (16/15)*pkt_rssi,
// this estimation looses one floating point
// operation, and should be precise enough.
pkt_rssi = (int)(1.066 * pkt_rssi);
}
return pkt_rssi;
}
uint8_t ISR_VECT sx127x::packetSnrRaw() { if (_frequency < 820E6) pkt_rssi -= 7;
return readRegister(REG_PKT_SNR_VALUE_7X);
}
float ISR_VECT sx127x::packetSnr() { if (pkt_snr < 0) { pkt_rssi += pkt_snr; }
return ((int8_t)readRegister(REG_PKT_SNR_VALUE_7X)) * 0.25; else {
// Slope correction is (16/15)*pkt_rssi,
// this estimation looses one floating point
// operation, and should be precise enough.
pkt_rssi = (int)(1.066 * pkt_rssi);
}
return pkt_rssi;
} }
uint8_t ISR_VECT sx127x::packetSnrRaw() { return readRegister(REG_PKT_SNR_VALUE_7X); }
float ISR_VECT sx127x::packetSnr() { return ((int8_t)readRegister(REG_PKT_SNR_VALUE_7X)) * 0.25; }
long sx127x::packetFrequencyError() { long sx127x::packetFrequencyError() {
int32_t freqError = 0; int32_t freqError = 0;
freqError = static_cast<int32_t>(readRegister(REG_FREQ_ERROR_MSB_7X) & B111); freqError = static_cast<int32_t>(readRegister(REG_FREQ_ERROR_MSB_7X) & B111);
@ -293,17 +269,13 @@ long sx127x::packetFrequencyError() {
size_t sx127x::write(uint8_t byte) { return write(&byte, sizeof(byte)); } size_t sx127x::write(uint8_t byte) { return write(&byte, sizeof(byte)); }
size_t sx127x::write(const uint8_t *buffer, size_t size) { size_t sx127x::write(const uint8_t *buffer, size_t size) {
int currentLength = readRegister(REG_PAYLOAD_LENGTH_7X); int currentLength = readRegister(REG_PAYLOAD_LENGTH_7X);
if ((currentLength + size) > MAX_PKT_LENGTH) { if ((currentLength + size) > MAX_PKT_LENGTH) { size = MAX_PKT_LENGTH - currentLength; }
size = MAX_PKT_LENGTH - currentLength;
}
for (size_t i = 0; i < size; i++) { for (size_t i = 0; i < size; i++) { writeRegister(REG_FIFO_7X, buffer[i]); }
writeRegister(REG_FIFO_7X, buffer[i]); writeRegister(REG_PAYLOAD_LENGTH_7X, currentLength + size);
}
writeRegister(REG_PAYLOAD_LENGTH_7X, currentLength + size); return size;
return size;
} }
int ISR_VECT sx127x::available() { return (readRegister(REG_RX_NB_BYTES_7X) - _packetIndex); } int ISR_VECT sx127x::available() { return (readRegister(REG_RX_NB_BYTES_7X) - _packetIndex); }

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sx127x.h
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@ -1,9 +1,6 @@
// Copyright (c) Sandeep Mistry. All rights reserved. // Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
// Licensed under the MIT license. // Licensed under the MIT license.
// Modifications and additions copyright 2024 by Mark Qvist
// Obviously still under the MIT license.
#ifndef SX1276_H #ifndef SX1276_H
#define SX1276_H #define SX1276_H

101
sx128x.cpp
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@ -1,11 +1,10 @@
// Copyright (c) Sandeep Mistry. All rights reserved. // Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
// Licensed under the MIT license. // Licensed under the MIT license.
// Modifications and additions copyright 2024 by Mark Qvist & Jacob Eva #include "Boards.h"
// Obviously still under the MIT license.
#if MODEM == SX1280
#include "sx128x.h" #include "sx128x.h"
#include "Boards.h"
#define MCU_1284P 0x91 #define MCU_1284P 0x91
#define MCU_2560 0x92 #define MCU_2560 0x92
@ -44,19 +43,19 @@
#define OP_STANDBY_8X 0x80 #define OP_STANDBY_8X 0x80
#define OP_TX_8X 0x83 #define OP_TX_8X 0x83
#define OP_RX_8X 0x82 #define OP_RX_8X 0x82
#define OP_SET_IRQ_FLAGS_8X 0x8D // also provides info such as #define OP_SET_IRQ_FLAGS_8X 0x8D // Also provides info such as
// preamble detection, etc for // preamble detection, etc for
// knowing when it's safe to switch // knowing when it's safe to switch
// antenna modes // antenna modes
#define OP_CLEAR_IRQ_STATUS_8X 0x97 #define OP_CLEAR_IRQ_STATUS_8X 0x97
#define OP_GET_IRQ_STATUS_8X 0x15 #define OP_GET_IRQ_STATUS_8X 0x15
#define OP_RX_BUFFER_STATUS_8X 0x17 #define OP_RX_BUFFER_STATUS_8X 0x17
#define OP_PACKET_STATUS_8X 0x1D // get snr & rssi of last packet #define OP_PACKET_STATUS_8X 0x1D // Get snr & rssi of last packet
#define OP_CURRENT_RSSI_8X 0x1F #define OP_CURRENT_RSSI_8X 0x1F
#define OP_MODULATION_PARAMS_8X 0x8B // bw, sf, cr, etc. #define OP_MODULATION_PARAMS_8X 0x8B // BW, SF, CR, etc.
#define OP_PACKET_PARAMS_8X 0x8C // crc, preamble, payload length, etc. #define OP_PACKET_PARAMS_8X 0x8C // CRC, preamble, payload length, etc.
#define OP_STATUS_8X 0xC0 #define OP_STATUS_8X 0xC0
#define OP_TX_PARAMS_8X 0x8E // set dbm, etc #define OP_TX_PARAMS_8X 0x8E // Set dbm, etc
#define OP_PACKET_TYPE_8X 0x8A #define OP_PACKET_TYPE_8X 0x8A
#define OP_BUFFER_BASE_ADDR_8X 0x8F #define OP_BUFFER_BASE_ADDR_8X 0x8F
#define OP_READ_REGISTER_8X 0x19 #define OP_READ_REGISTER_8X 0x19
@ -73,9 +72,9 @@
#define OP_FIFO_READ_8X 0x1B #define OP_FIFO_READ_8X 0x1B
#define IRQ_PREAMBLE_DET_MASK_8X 0x80 #define IRQ_PREAMBLE_DET_MASK_8X 0x80
#define REG_PACKET_SIZE 0x901 #define REG_PACKET_SIZE 0x901
#define REG_FIRM_VER_MSB 0x154 #define REG_FIRM_VER_MSB 0x154
#define REG_FIRM_VER_LSB 0x153 #define REG_FIRM_VER_LSB 0x153
#define XTAL_FREQ_8X (double)52000000 #define XTAL_FREQ_8X (double)52000000
#define FREQ_DIV_8X (double)pow(2.0, 18.0) #define FREQ_DIV_8X (double)pow(2.0, 18.0)
@ -93,24 +92,8 @@ extern SPIClass SPI;
sx128x::sx128x() : sx128x::sx128x() :
_spiSettings(8E6, MSBFIRST, SPI_MODE0), _spiSettings(8E6, MSBFIRST, SPI_MODE0),
_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _rxen(pin_rxen), _busy(LORA_DEFAULT_BUSY_PIN), _txen(pin_txen), _ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _rxen(pin_rxen), _busy(LORA_DEFAULT_BUSY_PIN), _txen(pin_txen),
_frequency(0), _frequency(0), _txp(0), _sf(0x05), _bw(0x34), _cr(0x01), _packetIndex(0), _implicitHeaderMode(0), _payloadLength(255), _crcMode(0), _fifo_tx_addr_ptr(0),
_txp(0), _fifo_rx_addr_ptr(0), _rxPacketLength(0), _preinit_done(false), _tcxo(false) { setTimeout(0); }
_sf(0x05),
_bw(0x34),
_cr(0x01),
_packetIndex(0),
_implicitHeaderMode(0),
_payloadLength(255),
_crcMode(0),
_fifo_tx_addr_ptr(0),
_fifo_rx_addr_ptr(0),
_rxPacketLength(0),
_preinit_done(false),
_tcxo(false)
{
// overide Stream timeout value
setTimeout(0);
}
bool ISR_VECT sx128x::getPacketValidity() { bool ISR_VECT sx128x::getPacketValidity() {
uint8_t buf[2]; uint8_t buf[2];
@ -472,23 +455,17 @@ float ISR_VECT sx128x::packetSnr() {
} }
long sx128x::packetFrequencyError() { long sx128x::packetFrequencyError() {
// TODO: implement this, page 120 of sx1280 datasheet // TODO: Implement this, page 120 of sx1280 datasheet
int32_t freqError = 0; int32_t freqError = 0;
const float fError = 0.0; const float fError = 0.0;
return static_cast<long>(fError); return static_cast<long>(fError);
} }
void sx128x::flush() { } void sx128x::flush() { }
int ISR_VECT sx128x::available() { return _rxPacketLength - _packetIndex; } int ISR_VECT sx128x::available() { return _rxPacketLength - _packetIndex; }
size_t sx128x::write(uint8_t byte) { return write(&byte, sizeof(byte)); } size_t sx128x::write(uint8_t byte) { return write(&byte, sizeof(byte)); }
size_t sx128x::write(const uint8_t *buffer, size_t size) { size_t sx128x::write(const uint8_t *buffer, size_t size) {
if ((_payloadLength + size) > MAX_PKT_LENGTH) { if ((_payloadLength + size) > MAX_PKT_LENGTH) { size = MAX_PKT_LENGTH - _payloadLength; }
size = MAX_PKT_LENGTH - _payloadLength;
}
writeBuffer(buffer, size); writeBuffer(buffer, size);
_payloadLength = _payloadLength + size; _payloadLength = _payloadLength + size;
return size; return size;
@ -716,7 +693,7 @@ void sx128x::setTxPower(int level, int outputPin) {
} }
tx_buf[0] = reg_value + 18; tx_buf[0] = reg_value + 18;
tx_buf[1] = 0xE0; // ramping time - 20 microseconds tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2); executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2);
// T3S3 SX1280 PA // T3S3 SX1280 PA
@ -795,7 +772,7 @@ void sx128x::setTxPower(int level, int outputPin) {
break; break;
} }
tx_buf[0] = reg_value; tx_buf[0] = reg_value;
tx_buf[1] = 0xE0; // ramping time - 20 microseconds tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
// For SX1280 boards with no specific PA requirements // For SX1280 boards with no specific PA requirements
#else #else
@ -803,7 +780,7 @@ void sx128x::setTxPower(int level, int outputPin) {
else if (level < -18) { level = -18; } else if (level < -18) { level = -18; }
_txp = level; _txp = level;
tx_buf[0] = level + 18; tx_buf[0] = level + 18;
tx_buf[1] = 0xE0; // ramping time - 20 microseconds tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
#endif #endif
executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2); executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2);
@ -821,7 +798,7 @@ void sx128x::setFrequency(uint32_t frequency) {
} }
uint32_t sx128x::getFrequency() { uint32_t sx128x::getFrequency() {
// we can't read the frequency on the sx1280 // We can't read the frequency on the sx1280
uint32_t frequency = _frequency; uint32_t frequency = _frequency;
return frequency; return frequency;
} }
@ -847,12 +824,6 @@ uint32_t sx128x::getSignalBandwidth() {
return 0; return 0;
} }
// TODO: Is this needed for SX1280?
void sx128x::handleLowDataRate() { }
// TODO: Check if there's anything the sx1280 can do here
void sx128x::optimizeModemSensitivity() { }
void sx128x::setSignalBandwidth(uint32_t sbw) { void sx128x::setSignalBandwidth(uint32_t sbw) {
if (sbw <= 203.125E3) { _bw = 0x34; } if (sbw <= 203.125E3) { _bw = 0x34; }
else if (sbw <= 406.25E3) { _bw = 0x26; } else if (sbw <= 406.25E3) { _bw = 0x26; }
@ -872,40 +843,22 @@ void sx128x::setCodingRate4(int denominator) {
setModulationParams(_sf, _bw, _cr); setModulationParams(_sf, _bw, _cr);
} }
void sx128x::handleLowDataRate() { } // TODO: Is this needed for SX1280?
void sx128x::optimizeModemSensitivity() { } // TODO: Check if there's anything the sx1280 can do here
uint8_t sx128x::getCodingRate4() { return _cr + 4; } uint8_t sx128x::getCodingRate4() { return _cr + 4; }
void sx128x::setPreambleLength(long length) { _preambleLength = length; setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode); }
void sx128x::setPreambleLength(long length) { void sx128x::setSyncWord(int sw) { } // TODO: Implement
_preambleLength = length; void sx128x::enableTCXO() { } // TODO: Need to check how to implement on sx1280
setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode); void sx128x::disableTCXO() { } // TODO: Need to check how to implement on sx1280
}
// TODO: Implement
void sx128x::setSyncWord(int sw) { }
// TODO: need to check how to implement on sx1280
void sx128x::enableTCXO() { }
// TODO: need to check how to implement on sx1280
void sx128x::disableTCXO() { }
void sx128x::sleep() { uint8_t byte = 0x00; executeOpcode(OP_SLEEP_8X, &byte, 1); } void sx128x::sleep() { uint8_t byte = 0x00; executeOpcode(OP_SLEEP_8X, &byte, 1); }
uint8_t sx128x::getTxPower() { return _txp; } uint8_t sx128x::getTxPower() { return _txp; }
uint8_t sx128x::getSpreadingFactor() { return _sf; } uint8_t sx128x::getSpreadingFactor() { return _sf; }
void sx128x::enableCrc() { _crcMode = 0x20; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); } void sx128x::enableCrc() { _crcMode = 0x20; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
void sx128x::disableCrc() { _crcMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); } void sx128x::disableCrc() { _crcMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
void sx128x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); } void sx128x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); }
void sx128x::explicitHeaderMode() { _implicitHeaderMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); } void sx128x::explicitHeaderMode() { _implicitHeaderMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
void sx128x::implicitHeaderMode() { _implicitHeaderMode = 0x80; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); } void sx128x::implicitHeaderMode() { _implicitHeaderMode = 0x80; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
void sx128x::dumpRegisters(Stream& out) { for (int i = 0; i < 128; i++) { out.print("0x"); out.print(i, HEX); out.print(": 0x"); out.println(readRegister(i), HEX); } }
void sx128x::dumpRegisters(Stream& out) {
for (int i = 0; i < 128; i++) { out.print("0x"); out.print(i, HEX); out.print(": 0x"); out.println(readRegister(i), HEX); }
}
sx128x sx128x_modem; sx128x sx128x_modem;
#endif

21
sx128x.h
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@ -1,9 +1,6 @@
// Copyright (c) Sandeep Mistry. All rights reserved. // Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
// Licensed under the MIT license. // Licensed under the MIT license.
// Modifications and additions copyright 2024 by Mark Qvist
// Obviously still under the MIT license.
#ifndef SX128X_H #ifndef SX128X_H
#define SX128X_H #define SX128X_H
@ -11,18 +8,16 @@
#include <SPI.h> #include <SPI.h>
#include "Modem.h" #include "Modem.h"
#define LORA_DEFAULT_SS_PIN 10 #define LORA_DEFAULT_SS_PIN 10
#define LORA_DEFAULT_RESET_PIN 9 #define LORA_DEFAULT_RESET_PIN 9
#define LORA_DEFAULT_DIO0_PIN 2 #define LORA_DEFAULT_DIO0_PIN 2
#define LORA_DEFAULT_RXEN_PIN -1 #define LORA_DEFAULT_RXEN_PIN -1
#define LORA_DEFAULT_TXEN_PIN -1 #define LORA_DEFAULT_TXEN_PIN -1
#define LORA_DEFAULT_BUSY_PIN -1 #define LORA_DEFAULT_BUSY_PIN -1
#define LORA_MODEM_TIMEOUT_MS 15E3 #define LORA_MODEM_TIMEOUT_MS 15E3
#define PA_OUTPUT_RFO_PIN 0
#define PA_OUTPUT_RFO_PIN 0 #define PA_OUTPUT_PA_BOOST_PIN 1
#define PA_OUTPUT_PA_BOOST_PIN 1 #define RSSI_OFFSET 157
#define RSSI_OFFSET 157
class sx128x : public Stream { class sx128x : public Stream {
public: public:

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